Optimizing the Control of a Hysteretic Power Converter at Low Duty Cycles

ABSTRACT

A method for controlling a current associated with a power converter may comprise controlling the current based on at least a peak current threshold level for the current and a valley current threshold level for the current, and further controlling the current based on a duration of time that the power converter spends in a switching state of the power converter.

RELATED APPLICATION

The present disclosure claims priority to U.S. Provisional PatentApplication Ser. No. 63/055,950 filed Jul. 24, 2020, which isincorporated by reference herein in its entirety.

FIELD OF DISCLOSURE

The present disclosure relates in general to circuits for electronicdevices, including without limitation personal audio devices such aswireless telephones and media players, and more specifically, toprediction of a load current and a control current in a power converterusing output voltage thresholds.

BACKGROUND

Personal audio devices, including wireless telephones, such asmobile/cellular telephones, cordless telephones, mp3 players, and otherconsumer audio devices, are in widespread use. Such personal audiodevices may include circuitry for driving a pair of headphones or one ormore speakers. Such circuitry often includes a speaker driver includinga power amplifier for driving an audio output signal to headphones orspeakers. Oftentimes, a power converter may be used to provide a supplyvoltage to a power amplifier in order to amplify a signal driven tospeakers, headphones, or other transducers. A switching power converteris a type of electronic circuit that converts a source of power from onedirect current (DC) voltage level to another DC voltage level. Examplesof such switching DC-DC converters include but are not limited to aboost converter, a buck converter, a buck-boost converter, an invertingbuck-boost converter, and other types of switching DC-DC converters.Thus, using a power converter, a DC voltage such as that provided by abattery may be converted to another DC voltage used to power the poweramplifier.

A power converter may be used to provide supply voltage rails to one ormore components in a device. Accordingly, it may be desirable toregulate an output voltage of a power converter with minimal ripple inthe presence of a time-varying current and power load.

SUMMARY

In accordance with the teachings of the present disclosure, one or moredisadvantages and problems associated with existing approaches toregulating an output voltage of a power converter may be reduced oreliminated.

In accordance with embodiments of the present disclosure, a method forcontrolling a current associated with a power converter may comprisecontrolling the current based on at least a peak current threshold levelfor the current and a valley current threshold level for the current,and further controlling the current based on a duration of time that thepower converter spends in a switching state of the power converter.

In accordance with these and other embodiments of the presentdisclosure, a control circuit for controlling a current associated witha power converter may include threshold-based control circuitryconfigured to control the current based on at least a peak currentthreshold level for the current and a valley current threshold level forthe current and timer-based control circuitry configured to control thecurrent based on a duration of time that the power converter spends in aswitching state of the power converter.

In accordance with embodiments of the present disclosure, a device mayinclude a power converter and a control circuit for controlling acurrent associated with the power converter. The control circuit mayinclude threshold-based control circuitry configured to control thecurrent based on at least a peak current threshold level for the currentand a valley current threshold level for the current and timer-basedcontrol circuitry configured to control the current based on a durationof time that the power converter spends in a switching state of thepower converter.

Technical advantages of the present disclosure may be readily apparentto one skilled in the art from the figures, description and claimsincluded herein. The objects and advantages of the embodiments will berealized and achieved at least by the elements, features, andcombinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are examples and explanatory and arenot restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments and advantagesthereof may be acquired by referring to the following description takenin conjunction with the accompanying drawings, in which like referencenumbers indicate like features, and wherein:

FIG. 1 illustrates an example mobile device, in accordance withembodiments of the present disclosure;

FIG. 2 illustrates a block diagram of selected components internal to amobile device, in accordance with embodiments of the present disclosure;

FIG. 3A illustrates a block diagram of selected components of an exampleboost converter with multiple modes of operation depicting operation ina bypass mode, in accordance with embodiments of the present disclosure;

FIG. 3B illustrates a block diagram of selected components of an exampleboost converter with multiple modes of operation depicting operation ina boost active mode, in accordance with embodiments of the presentdisclosure;

FIG. 3C illustrates a block diagram of selected components of an exampleboost converter with multiple modes of operation depicting operation ina boost inactive mode, in accordance with embodiments of the presentdisclosure;

FIG. 4 illustrates a graph of inductor current through a phase of aboost converter and a control signal of switches of the phase versustime, in accordance with embodiments of the present disclosure;

FIG. 5 illustrates a block diagram of selected components of an examplecontrol circuit for a boost converter, in accordance with embodiments ofthe present disclosure;

FIG. 6 illustrates an example graph of a supply voltage generated by theboost converter of FIGS. 3A-3C versus time, in accordance with thepresent disclosure;

FIG. 7 illustrates a waveform of a supply voltage generated by a powerconverter over a period of time and a waveform of an inductor currentwithin the power converter over the same period of time, in accordancewith the present disclosure;

FIG. 8 illustrates a block diagram of selected components of an outercontrol loop subsystem of the current controller shown in FIG. 5 , inaccordance with embodiments of the present disclosure;

FIG. 9 illustrates example waveforms depicting an example of outer loopcontrol for a boost converter, in accordance with embodiments of thepresent disclosure;

FIG. 10 illustrates a block diagram of selected components of an innercontrol loop subsystem of the current controller shown in FIG. 5 , inaccordance with embodiments of the present disclosure;

FIG. 11 illustrates example waveforms depicting an example of inner loopcontrol for a boost converter, in accordance with embodiments of thepresent disclosure;

FIG. 12 illustrates example waveforms depicting an example of inner loopcontrol for a boost converter in light-load scenarios, in accordancewith embodiments of the present disclosure;

FIG. 13 illustrates a block diagram of selected components of anotherexample control circuit for a boost converter, in accordance withembodiments of the present disclosure;

FIG. 14 illustrates a block diagram of selected components of an innercontrol loop subsystem of the current controller shown in FIG. 13 , inaccordance with embodiments of the present disclosure;

FIG. 15 illustrates a block diagram of selected components of an outercontrol loop subsystem of the current controller shown in FIG. 13 , inaccordance with embodiments of the present disclosure;

FIG. 16 illustrates a block diagram of selected components of an examplepeak/valley controller, in accordance with embodiments of the presentdisclosure;

FIG. 17A illustrates a graph of an example waveform for boost converterinductor current for typical duty cycles of a boost converter, inaccordance with embodiments of the present disclosure;

FIG. 17B illustrates graphs of example waveforms for boost converterinductor current for very low duty cycles of a boost converter, inaccordance with embodiments of the present disclosure;

FIG. 18A illustrates graphs of example waveforms for an output currentof a boost converter, boost converter inductor current, and an outputvoltage of the boost converter for typical duty cycles of a boostconverter in response to a step in output current of the boostconverter, in accordance with embodiments of the present disclosure;

FIG. 18B illustrates graphs of example waveforms for an output currentof a boost converter, boost converter inductor current, and an outputvoltage of the boost converter for very low duty cycles of a boostconverter in response to a step in output current of the boostconverter, in accordance with embodiments of the present disclosure;

FIG. 19 illustrates a block diagram of selected components of an examplepeak/valley controller with further improvements over the examplepeak/valley controller of FIG. 16 , in accordance with embodiments ofthe present disclosure;

FIG. 20 illustrates graphs of example waveforms for an output current ofa boost converter, boost converter inductor current, a timer counter,and a timer output signal for very low duty cycles of a boost converterusing the example peak/valley controller shown in FIG. 19 , in responseto a step in output current of the boost converter, in accordance withembodiments of the present disclosure;

FIG. 21 illustrates a block diagram of selected components of an examplepeak/valley controller with further improvements over the examplepeak/valley controllers of FIG. 16 and FIG. 19 , in accordance withembodiments of the present disclosure; and

FIG. 22 illustrates a block diagram of selected components of an examplepeak/valley controller with further improvements over the examplepeak/valley controllers of FIG. 16 , FIG. 20 , and FIG. 21 , inaccordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates an example mobile device 1, in accordance withembodiments of the present disclosure. FIG. 1 depicts mobile device 1coupled to a headset 3 in the form of a pair of earbud speakers 8A and8B. Headset 3 depicted in FIG. 1 is merely an example, and it isunderstood that mobile device 1 may be used in connection with a varietyof audio transducers, including without limitation, headphones, earbuds,in-ear earphones, and external speakers. A plug 4 may provide forconnection of headset 3 to an electrical terminal of mobile device 1.Mobile device 1 may provide a display to a user and receive user inputusing a touch screen 2, or alternatively, a standard liquid crystaldisplay (LCD) may be combined with various buttons, sliders, and/ordials disposed on the face and/or sides of mobile device 1.

FIG. 2 illustrates a block diagram of selected components integral tomobile device 1, in accordance with embodiments of the presentdisclosure. As shown in FIG. 2 , mobile device 1 may include a boostconverter 20 configured to boost a battery voltage V_(BAT) to generate asupply voltage V_(SUPPLY) to a plurality of downstream components 18 ofmobile device 1. Downstream components 18 of mobile device 1 may includeany suitable functional circuits or devices of mobile device 1,including without limitation processors, audio coder/decoders,amplifiers, display devices, etc. As shown in FIG. 2 , mobile device 1may also include a battery charger 16 for recharging battery 22.

In some embodiments of mobile device 1, boost converter 20 and batterycharger 16 may comprise the only components of mobile device 1electrically coupled to battery 22, and boost converter 20 mayelectrically interface between battery 22 and all downstream components18 of mobile device 1. However, in other embodiments of mobile device 1,some downstream components 18 may electrically couple directly tobattery 22.

FIG. 3A illustrates a block diagram of selected components of an exampleboost converter 20 with multiple modes of operation depicting operationin a bypass mode, in accordance with embodiments of the presentdisclosure. As shown in FIG. 3A, boost converter 20 may include abattery 22, a plurality of inductive boost phases 24, a sense capacitor26, a sense resistor 28, a bypass switch 30, and a control circuit 40.As shown in FIG. 3A, each inductive boost phase 24 may include a powerinductor 32, a charge switch 34, a rectification switch 36, and outputcapacitor 38.

Although FIGS. 3A-3C depict boost converter 20 having three inductiveboost phases 24, embodiments of boost converter 20 may have any suitablenumber of inductive boost phases 24. In some embodiments, boostconverter 20 may comprise three or more inductive boost phases 24. Inother embodiments, boost converter 20 may comprise fewer than threephases (e.g., a single phase or two phases).

Boost converter 20 may operate in the bypass mode when supply voltageV_(SUPPLY) generated by boost converter 20 is greater than a thresholdminimum voltage V_(MIN). In some embodiments, such threshold minimumvoltage V_(MIN) may be a function of a monitored current (e.g., acurrent through sense resistor 28). In some embodiments, such thresholdminimum voltage V_(MIN) may be varied in accordance with variations inthe monitored current, in order to provide desired headroom fromcomponents supplied from supply voltage V_(SUPPLY). Control circuit 40may be configured to sense supply voltage V_(SUPPLY) and compare supplyvoltage V_(SUPPLY) to threshold minimum voltage V_(MIN). In the eventthat supply voltage V_(SUPPLY) and voltage VDD_SENSE across sensecapacitor 26 are greater than threshold minimum voltage V_(MIN), controlcircuit 40 may activate (e.g., enable, close, turn on) bypass switch 30and one or more rectification switches 36 and deactivate (e.g., disable,open, turn off) charge switches 34. In such bypass mode, the resistancesof rectification switches 36, power inductors 32, and bypass switch 30may combine to minimize a total effective resistance of a path betweenbattery 22 and supply voltage V_(SUPPLY).

FIG. 3B illustrates a block diagram of selected components of exampleboost converter 20 depicting operation in a boost active mode, inaccordance with embodiments of the present disclosure. In the boostactive mode, control circuit 40 may deactivate (e.g., disable, open,turn off) bypass switch 30, and periodically commutate charge switches34 (e.g., during a charging state of an inductive boost phase 24) andrectification switches 36 (e.g., during a transfer state of an inductiveboost phase 24) of inductive boost phase 24 (as described in greaterdetail below) by generating appropriate control signals P₁,

, P₂,

, P₃, and

, to deliver a current I_(BAT) and boost battery voltage V_(BAT) to ahigher supply voltage V_(SUPPLY) in order to provide a programmed (orservoed) desired current (e.g., average current) to the electrical nodeof supply voltage V_(SUPPLY) , while maintaining supply voltageV_(SUPPLY) above threshold minimum voltage V_(MIN). For example, controlcircuit 40 may operate in the boost active mode to maintain an inductorcurrent I_(L) (e.g., I_(L1), I_(L2), I_(L3)) between a peak current anda valley current as described in U.S. patent application Ser. No.17/119,517 filed Dec. 11, 2020, and incorporated by reference herein inits entirety. In the boost active mode, control circuit 40 may operateboost converter 20 by operating inductive boost phase 24 in a peak andvalley detect operation, as described in greater detail below. Theresulting switching frequency of charge switches 34 and rectificationswitches 36 of inductive boost phase 24 may be determined by the sensevoltage VDD_SENSE, supply voltage V_(SUPPLY), an inductance of powerinductor 32A, and a programmed ripple parameter (e.g., a configurationof a target current ripple for an inductor current I_(L)).

FIG. 3C illustrates a block diagram of selected components of boostconverter 20 depicting operation in a boost inactive mode, in accordancewith embodiments of the present disclosure. Boost converter 20 mayoperate in the boost inactive mode when supply voltage V_(SUPPLY)generated by boost converter 20 rises above hysteresis voltage V_(HYST)and a sense voltage VDD_SENSE remains below supply voltage V_(SUPPLY).In the boost inactive mode, control circuit 40 may deactivate (e.g.,disable, open, turn off) bypass switch 30, charge switches 34, andrectification switches 36. Thus, when sense voltage VDD_SENSE remainsbelow supply voltage V_(SUPPLY), control circuit 40 prevents boostconverter 20 from entering the bypass mode in order to not backpowerbattery 22 from supply voltage V_(SUPPLY). Further, if supply voltageV_(SUPPLY) should fall below threshold minimum voltage V_(MIN), controlcircuit 40 may cause boost converter 20 to again enter the boost activemode in order to maintain supply voltage V_(SUPPLY) between thresholdminimum voltage V_(MIN) and hysteresis voltage V_(HYST).

As described above, when boost converter 20 operates in the boost activemode, control circuit 40 may provide hysteretic current control ofinductor currents I_(L1), I_(L2), and I_(L3) through power inductors32A, 32B, and 32C, respectively. FIG. 4 illustrates an example graph ofinductor current I_(L1) and control signal P₁ versus time, in accordancewith embodiments of the present disclosure. As shown in FIG. 4 , controlcircuit 40 may generate control signals P₁ and

of inductive boost phase 24A such that: (a) when inductor current I_(L1)falls below a valley current threshold I_(val1), control circuit 40 mayactivate charge switch 34A and deactivate rectification switch 36A; and(b) when inductor current I_(L1) increases above a peak currentthreshold I_(pk1), control circuit 40 may deactivate charge switch 34Aand activate rectification switch 36A. Accordingly, control circuit 40may provide hysteretic control of inductor current I_(L1) such thatinductor current I_(L1) varies between approximately valley currentthreshold I_(val1) and approximately peak current threshold I_(pk1),with inductor current I_(L1) having an average current I_(avg1) and aripple current I_(ripple), such that:

${I_{{pk}1} = {I_{{avg}1} + \frac{I_{ripple}}{2}}};{and}$$I_{{val}1} = {I_{{avg}1} - {\frac{I_{ripple}}{2}.}}$

Control circuit 40 may also generate control signals P₂,

, P₃, and

of inductive boost phases 24B and 24C to provide similar or identicalcontrol of inductor currents I_(L2) and I_(L3).

FIG. 5 illustrates a block diagram of selected components of controlcircuit 40, in accordance with embodiments of the present disclosure. Asshown in FIG. 5 , control circuit 40 may comprise a plurality ofcomparators 42A, 42B, 42C, and 42D, each configured to compare supplyvoltage V_(SUPPLY) to a respective threshold voltage V₁, V₂, V₃, and V₄,and generate respective comparison signals C₁, C₂, C₃, and C₄.

Based on comparison signals C₁, C₂, C₃, and C₄, a load estimator 44 ofcontrol circuit 40 may implement an inner control loop to estimate aload seen at the output of boost converter 20, and based thereon,generate a target average current I_(avg) for battery current I_(BAT).The inner control loop may be said to provide continuous control ofinductor current I_(L). Further, based on comparison signals C₁, C₂, andC₄, and target average current I_(avg), a current controller 46 ofcontrol circuit 40 may implement an outer control loop. Both the innercontrol loop and outer control loop may be used to set valley currentthreshold I_(val), peak current threshold I_(pk), and a control signalENABLE for selectively enabling or disabling the boost active mode ofboost converter 20. In operation, the inner control loop may maximizeefficiency of boost converter 20 and minimize ripple on voltageV_(SUPPLY), while the outer control loop may bound a maximum ripple ofsupply voltage V_(SUPPLY) Based on valley current threshold I_(val) andpeak current threshold I_(pk), a peak/valley controller 48 of controlcircuit 40 may generate control signals for controlling boost converter20.

FIG. 6 illustrates an example graph of supply voltage V_(SUPPLY) versustime, in accordance with the present disclosure. As shown in FIG. 6 ,threshold voltages V₁, V₂, V₃, and V₄ may divide the magnitude of supplyvoltage V_(SUPPLY) into five distinct regions A, B, C, D, and E. FIG. 6demonstrates how load estimator 44 may adjust target average currentI_(avg) in each of these five distinct regions A, B, C, D, and E.

Region A may be referred to as the MAX region. Is this region, supplyvoltage V_(SUPPLY) is below an undervoltage threshold represented bythreshold voltage V₁. Accordingly, in Region A, load estimator 44 mayset target average current I_(avg) to its maximum in order to causegeneration of as much inductor current I_(L) (e.g., I_(L1), I_(L2),I_(L3)) as possible in order to minimize droop of supply voltageV_(SUPPLY).

Region B may be referred to as the INCREMENT region. In this regionbetween threshold voltages V₁ and V₂, load estimator 44 may recursivelyincrement target average current I_(avg) in order to increase currentdelivered by boost converter 20 in order to increase supply voltageV_(SUPPLY) Load estimator 44 may increment target average currentI_(avg) using multiplicative recursion (e.g.,I_(avg(i+1))=I_(avg(i))×a₁, where a₁>1), additive recursion (e.g.,I_(avg(i+1))=I_(avg(i))+a₂, where a₂>0), or any other recursiveapproach.

Region C may be referred to as the MEASURE region, in which V_(SUPPLY)is between threshold voltages V₂ and V₃. In Region C, load estimator 44may measure a time in which supply voltage V_(SUPPLY) takes to crossthreshold voltages V₂ and V₃ and may update target average currentI_(avg) accordingly, as described in greater detail below.

Region D may be referred to as the DECREMENT region. In this regionbetween threshold voltages V₃ and V₄, load estimator 44 may recursivelydecrement target average current I_(avg) in order to decrease currentdelivered by boost converter 20 in order to decrease supply voltageV_(SUPPLY). Load estimator 44 may decrement target average currentI_(avg) using multiplicative recursion (e.g.,I_(avg(i+1))=I_(avg(i))×a₁, where a₁<1), additive recursion (e.g.,I_(avg(i+1))=I_(avg(i))a₂, where a₂<0), or any other recursive approach.

Region E may be referred to as the HOLD region. In this region abovethreshold voltage V₄, load estimator 44 may hold or maintain the valueof decrement target average current I_(avg) (e.g.,I_(avg(i+1))=I_(avg(i)))

As discussed above, when in Region C, load estimator 44 measures thetime supply voltage V_(SUPPLY) takes to cross threshold voltages V₂ andV₃, and may use such measurement to update target average currentI_(avg). To illustrate, reference is made to FIG. 7 which depicts awaveform of supply voltage V_(SUPPLY) over a period of time and awaveform of an inductor current I_(L) (e.g., one of inductor currentsI_(L1), I_(L2), I_(L3)) over the same period of time. As shown in FIG. 7, load estimator 44 may measure a time Δt₁ it takes supply voltageV_(SUPPLY) to increase from threshold voltage V₂ to threshold voltageV₃. The change in voltage from threshold voltage V₂ to threshold voltageV₃ divided by the time Δt₁ may define a slope s₁. Similarly, loadestimator 44 may measure a time Δt₂ it takes supply voltage V_(SUPPLY)to decrease from threshold voltage V₃ to threshold voltage V₂. Thechange in voltage from threshold voltage V₃ to threshold voltage V₂divided by the time Δt₂ may define a slope s₂. Average inductor currentI_(avg(i)) through an individual power inductor 32 during a risingsupply voltage V_(SUPPLY) may be defined as a rise current I_(R), whileaverage inductor current I_(avg(i)) through an individual power inductor32 during a falling supply voltage V_(SUPPLY) may be defined as a fallcurrent I_(F).

Using a charge balance relationship for output capacitor 38 coupled tosupply voltage V_(SUPPLY), load estimator 44 may update target averagecurrent I_(avg) drawn from battery 22. For example, using themeasurement for rise current I_(R), target average current I_(avg) maybe updated in accordance with:

$I_{avg} = {I_{R} - {s_{1} \cdot \frac{C_{out}}{D_{i}^{\prime}}}}$

Where D_(i) ^(′) is equal to one minus the duty cycle of inductorcurrent I_(L) and C_(out) is a capacitance of output capacitor 38. Thequotient

$\frac{C_{out}}{D_{i}^{\prime}}$

may be unknown or uncertain, but may be estimated. For example, in someembodiments, load estimator 44 may estimate the quotient

$\frac{C_{out}}{D_{i}^{\prime}}$

using fixed values. However, if an input voltage (e.g., voltageVDD_SENSE) is known, the inverse of D_(i) ^(′) may be approximatelyequal to the quotient of supply voltage V_(SUPPLY) divided by such inputvoltage. Thus, the foregoing equation for updating target averagecurrent I_(avg) may be written:

$I_{avg} = {I_{R} - {s_{1} \cdot \frac{V_{SUPPLY}}{VDD\_ SENSE} \cdot C_{out}}}$

However, such relationship may have uncertainty due to the approximationof output capacitance C_(out) and the assumption that boost converter 20is lossless. But, such uncertainty may be eliminated by using bothmeasurements for rise current I_(R) and fall current I_(F), as given bythe equation:

$I_{avg} = {I_{F} - {\frac{s_{2}}{s_{1} - s_{2}} \cdot \left( {I_{R} - I_{F}} \right)}}$

If it is assumed that the increase in voltage from threshold voltage V₂to threshold voltage V₃ is equal in magnitude to the decrease in voltagefrom threshold voltage V₃ to threshold voltage V₂, then the foregoingequation for updating target average current I_(avg) may be written:

$I_{avg} = {\left( \frac{I_{R}}{\frac{\Delta t_{2}}{\Delta t_{1}} + 1} \right) + {\left( {1 - \frac{1}{\frac{\Delta t_{2}}{\Delta t_{1}} + 1}} \right)I_{F}}}$

The two approaches above for updating target average current I_(avg) mayeach have their own advantages and disadvantages. For example, theupdate based on one current measurement may be better at detectinglarge, fast transients, but could be inaccurate due to assumptionsregarding the duty cycle and output capacitance C_(out), and alsoassumes that changes in voltage and measurements of current are knownexactly. The update based on two current measurements may be more robustagainst offsets in the changes in voltage and measurements of current,but such approach assumes the load of boost converter 20 is fixed overboth measurements, which may not be the case, especially in the presenceof large transients. Thus, in some embodiments, a hybrid approach may beused in which the single-measurement approach is used if only onemeasurement is available or if the single measurement is larger (orsmaller) than the dual measurement by more than the band of uncertaintyof the single-measurement approach, and the dual-measurement approach isused otherwise.

FIG. 8 illustrates a block diagram of selected components of an outerloop control subsystem 50 of current controller 46, in accordance withembodiments of the present disclosure. As shown in FIG. 8 , currentcontroller 46 may be implemented using logic inverters 52A and 52B,set-reset latches 54A and 54B, and multiplexers 56A and 56B.

Logic inverter 52A may invert comparison signal C2 and set-reset latch54A may hysteretically generate control signal ENABLE such that controlsignal ENABLE is asserted when supply voltage V_(SUPPLY) falls belowthreshold voltage V₂ and is deasserted when supply voltage V_(SUPPLY)rises above threshold voltage V₄. When control signal ENABLE isdeasserted, control circuit 40 may disable charge switches 34 andrectification switches 36 and boost converter 20 may be operated in theboost inactive mode.

Further, inverter 52B may invert comparison signal C₁ and set-resetlatch 54B may hysteretically generate control signal MAX_ENABLE thatindicates whether a maximum for target average current I_(avg) should begenerated by control circuit 40. Receipt of control signal RESET_MAX maydeassert control signal MAX_ENABLE, to return control of peak currentthreshold I_(pk) and valley current threshold I_(val) to the innercontrol loop. Multiplexer 56A may, based on control signal MAX_ENABLE, amaximum for peak current threshold I_(pk) and a target peak currentthreshold I_(pk) (e.g., derived from target average current I_(avg)calculated by load estimator 44), generate a peak current thresholdI_(pk). Similarly, multiplexer 56B may, based on control signalMAX_ENABLE, a maximum for valley current threshold I_(val), and a targetvalley current threshold I_(val) (e.g., derived from target averagecurrent L_(avg) calculated by load estimator 44), generate a valleycurrent threshold I_(val).

To further illustrate outer loop control by current controller 46,reference is made to FIG. 9 . As shown in FIG. 9 , in Region I of thewaveforms, supply voltage V_(SUPPLY) exceeds threshold voltage V₄, andboost converter 20 may be placed in the boost inactive mode as set-resetlatch 54A may cause control signal ENABLE to be deasserted, leavingboost converter 20 with a high-impedance. Accordingly, in Region I, theload of boost converter 20 may cause a decrease in supply voltageV_(SUPPLY).

When supply voltage V_(SUPPLY) decreases below threshold voltage V₂,set-reset latch 54A may cause control signal ENABLE to be asserted, andboost converter 20 may enter the boost active mode. In Region II of thewaveforms shown in FIG. 9 , load estimator 44 may in effect control peakcurrent threshold I_(pk) and valley current threshold I_(val), throughthe estimate of target average current I_(avg) performed by loadestimator 44. However, in the specific example shown in FIG. 9 , loadestimator 44 may not “turn around” supply voltage V_(SUPPLY) quickenough, and supply voltage V_(SUPPLY) may continue to decrease.

Accordingly, supply voltage V_(SUPPLY) may decrease below thresholdvoltage V₁, thus causing set-reset latch 54B to set, asserting controlsignal MAX_ENABLE, forcing peak current I_(pk) and target valley currentI_(val) to their maximum values (maximum peak current I_(pk-max) andmaximum valley current I_(avg-max)) in Region III of FIG. 9 . Aftersufficient increase in supply voltage V_(SUPPLY), set-reset latch 54Bmay reset and deassert control signal MAX_ENABLE, and load estimator 44may again regain control as shown in Region IV of the waveforms. Ifsupply voltage V_(SUPPLY) increases further again in excess of thresholdvoltage V₄, set-reset latch 54A may again deassert control signalENABLE, causing boost converter 20 to enter the boost inactive mode.

Accordingly, the outer loop implemented by current controller 46 maytoggle boost converter 20 between a maximum current and high-impedancestate, and bound a ripple in supply voltage V_(SUPPLY) to approximatelybetween threshold voltages V₁ and V₄ even when inner loop control ofload estimator 44 fails to regulate supply voltage V_(SUPPLY).

FIG. 10 illustrates a block diagram of selected components of an innercontrol loop subsystem 60 of current controller 46, in accordance withembodiments of the present disclosure. FIG. 11 illustrates examplewaveforms depicting examples of inner loop control for boost converter20, in accordance with embodiments of the present disclosure.

As shown in FIG. 10 , inner control loop subsystem 60 may receive targetaverage current I_(avg) calculated by load estimator 44, divide suchtarget average current I_(avg) by a number n of inductive boost phase 24present in boost converter 20, and apply each of a positive offset +Δand a negative offset −Δ to target average current I_(avg)/n by offsetblocks 62A and 62B, respectively. The results of offset blocks 62A and62B may be respectively saturated to a minimum value by saturationblocks 64A and 64B to generate rise current I_(R) and fall currentI_(F), respectively. Adder blocks 68A and 68B may add one-half of ripplecurrent I_(ripple) to each of rise current I_(R) and fall current I_(F)and adder blocks 70A and 70B may subtract one-half of ripple currentI_(ripple) from each of rise current I_(R) and fall current I_(F). Basedon comparison signals C₂ and C₃, latch 66 may selectively assert anddeassert control signal TOGGLE to toggle selection of multiplexers 72Aand 72B to:

-   -   In the event control signal TOGGLE is asserted due to supply        voltage V_(SUPPLY) decreasing below threshold voltage V₂,        generate an intermediate peak current threshold I_(pk) ^(′) and        an intermediate valley current threshold I_(val) ^(′) such that        I_(pk) ^(′)=I_(R)+I_(ripple)/2 and I_(val)        ^(′)=I_(R)−I_(ripple)/2, and the mean inductor current is rise        current I_(R).    -   In the event control signal TOGGLE is deasserted due to supply        voltage V_(SUPPLY) increasing above threshold voltage V₃,        generate intermediate peak current threshold I_(pk) ^(′) and        intermediate valley current threshold I_(val) ^(′) such that        I_(pk) ^(′)=I_(F)+I_(ripple)/2 and I_(val)        ^(′)=I_(F)−I_(ripple)/2, and the mean inductor current is fall        current I_(F).

As shown in FIG. 8 above, intermediate peak current threshold I_(pk)^(′) and intermediate valley current threshold I_(val) ^(′) may be usedby outer loop control subsystem 50 to generate peak current thresholdI_(pk) and valley current threshold I_(val).

Thus, toggling of control signal TOGGLE may maintain regulation ofV_(SUPPLY) between threshold voltage V₂ and threshold voltage V₃, asshown in FIG. 11 . For example, when control signal TOGGLE is high, theaverage per phase current may be set to rise current I_(R). Because thisvalue of current is offset from target average current I_(avg) bypositive offset +Δ, it may cause supply voltage V_(SUPPLY) to rise. Onthe other hand, when control signal TOGGLE is low, the average per phasecurrent may be set to fall current I_(F). Because this value of currentis offset from target average current I_(avg) by negative offset −Δ, itmay cause supply voltage V_(SUPPLY) to fall.

Occasionally, a change in loading at the output of boost converter 20may lead to a change in target average current I_(avg), as shown at timeto in FIG. 11 , in which case load estimator 44 may modify targetaverage current I_(avg) as described above.

FIG. 12 illustrates example waveforms depicting examples of inner loopcontrol for boost converter 20 in light-load scenarios, in accordancewith embodiments of the present disclosure. For light-loads, targetaverage current I_(avg) calculated by load estimator 44 may be largerthan a minimum target average current I_(avg_min) applied by saturationsblocks 64A and 64B. Because rise current I_(R) and fall current I_(F)may be saturated in this scenario, inductor current I_(L) may be largerthan is required for steady-state operation of boost converter 20,forcing supply voltage V_(SUPPLY) to have a positive slope in Regions Iand III of FIG. 12 . When supply voltage V_(SUPPLY) crosses abovethreshold voltage V₄, set-reset latch 54A from outer loop controlsubsystem 50 may cause boost converter 20 to enter the boost inactiveregion, thus leading to forcing supply voltage V_(SUPPLY) to have anegative slope in Regions II and IV of FIG. 12 due to the high-impedancestate of boost converter 20. In light-load conditions, toggling betweenthe boost active state and the boost inactive state with fixedsaturation thresholds for peak current threshold I_(pk) and valleycurrent threshold I_(val) may maximize power efficiency.

In a simple implementation of control circuit 40, control circuit 40 maybe implemented as a digital control system that sets control parametersfor peak current threshold I_(pk), valley current threshold I_(val),control signal ENABLE, and the number n of inductive boost phases 24enabled. However, due to sample-and-hold circuitry that may be employedin such digital implementation and incumbent processing delays, severalclock cycles of delay may occur between when comparators 42 toggle andwhen new control parameters are determined. Such delay may contribute toovershoot and undershoot in supply voltage V_(SUPPLY) generated by boostconverter 20, which may lead to undesirable ripple and excessive voltagedroop on supply voltage VsuPPLY It may be desirable to have a fasterresponse to quick load transients on supply voltage V_(SUPPLY) comparedto that which could be supported by a fully digital implementation ofcontrol circuit 40.

FIG. 13 illustrates a block diagram of selected components of controlcircuit 40A, in accordance with embodiments of the present disclosure.Control circuit 40A may be functionally and/or structurally similar inmany respects to control circuit 40 shown in FIG. 5 , with a maindifference being that current controller 46A is split into a digitalcalculation block 82 and an analog circuit 84. As described in greaterdetail below, analog circuit 84 may minimize delays that would bepresent in a fully-digital implementation by using pre-seeded values forcontrol parameters generated by digital calculation block 82 andselecting among such pre-seeded values by analog circuit 84 in order togenerate control parameters communicated to peak/valley controller 48and boost converter 20. Analog circuit 84 may be driven directly bycomparators 42, such that when comparators 42 toggle, analog circuit 84immediately changes state and chooses generated new control parametersfor peak current threshold I_(pk), valley current threshold I_(val),control signal ENABLE, and the number n of inductive boost phases 24enabled. Such manner of changing states and updating control parametersmay create a low-latency path from comparators 42 to new, updatedcontrol parameters. On the other hand, digital calculation block 82 maybe configured to calculate the pre-seeded parameters based on theoutputs of comparators 42 and its internal control algorithm.

FIG. 14 illustrates a block diagram of selected components of an innercontrol loop subsystem 60A of current controller 46A, in accordance withembodiments of the present disclosure. Inner control loop subsystem 60Amay be functionally and/or structurally similar in many respects toinner loop control subsystem 60 shown in FIG. 10 , except thatmultiplexers 72A and 72B and a portion of analog state machine 80 may beimplemented by analog circuit 84, and other components of inner loopcontrol subsystem 60A may be implemented by digital calculation block82. As shown in FIG. 14 , digital calculation block 82 may generatepre-seeded values based on all comparison signals C₁, C₂, C₃, and C₄,and analog state machine 80 may be configured to, based on comparisonsignals C₂ and C₃, control selection of such pre-seeded values withmultiplexers 72A and 72B in order to generate intermediate peak currentthreshold I_(pk) ^(′) and intermediate valley current threshold I_(val)^(′).

FIG. 15 illustrates a block diagram of selected components of an outerloop control subsystem 50A of current controller 46A, in accordance withembodiments of the present disclosure. Outer loop control subsystem 50Amay be functionally and/or structurally similar in many respects toouter loop control subsystem 50 shown in FIG. 8 , except thatmultiplexers 56A and 56B and a portion of analog state machine 86 may beimplemented by analog circuit 84. As shown in FIG. 15 , analog statemachine 86 may be configured to, based on comparison signal C₁ and acontrol signal RESET_MAX generated by digital calculation block 82,control between selection of pre-seeded values for maximum peak currentthreshold I_(pk_max) and maximum valley current threshold I_(val_max) onthe one hand and intermediate peak current threshold I_(pk) ^(′) andintermediate valley current threshold I_(val) ^(′) generated by innercontrol loop subsystem 60A on the other hand. Further, analog statemachine 86 may be configured to, based on comparison signals C₂ and C₄,control signal ENABLE for boost converter 20.

In a boost converter 20 having multiple inductive boost phases 24, allinductive boost phases 24 may use identical set points for peak currentthreshold I_(pk) and valley current threshold I_(val), and a lookuptable or other suitable approach may be used to determine how manyinductive boost phases 24 are active based on target average currentI_(avg). Further, such lookup table or other suitable approach may havehysteresis to prevent excessive enabling and disabling of an individualinductive boost phase 24. In addition, the lookup table or anotherlookup table may be used to determine how many inductive boost phases 24are to be enabled in a maximum current state of boost converter 20(e.g., supply voltage V_(SUPPLY)<threshold voltage V₁).

Although the foregoing discussion contemplates current control andvoltage regulation of a boost converter 20, it is understood thatsimilar or identical approaches may be applied to other types ofinductor-based power converters, including without limitation buckconverters and buck-boost converters.

Referring back to FIGS. 3A-3C, each power inductor 32 of respectiveinductive boost phases 24 may draw a respective inductor current I_(L)(e.g., I_(L1), I_(L2), and I_(L3)). Also, because all inductive boostphases 24 may use identical set points for peak current threshold I_(pk)and valley current threshold I_(val) as described above, inductorcurrents I_(L1), I_(L2), and I_(L3) would all be expected to be in phasewith one another in the event that impedances of each inductive boostphase 24 were identical. However, in practical implementation, ifimpedances of each inductive boost phase 24 are different but close invalue, the respective inductor currents I_(L1), IL₂, and I_(L3) mayslowly drift in and out of phase with one another. But relatively longperiods may exist when two or more of respective inductor currentsI_(L1), I_(L2), and I_(L3) are in phase with one another.

FIG. 16 illustrates a block diagram of selected components of apeak/valley controller 48A, in accordance with embodiments of thepresent disclosure. In some embodiments, peak/valley controller 48A maybe used to implement peak/valley controller 48 shown in FIG. 5 . Asshown in FIG. 16 , peak/valley controller 48A may include comparators90A and 90B and latch 92. Comparator 90A may be configured to compare aninductor current I_(L) to valley current threshold I_(val), whilecomparator 90B may be configured to compare an inductor current I_(L) topeak current threshold I_(pk). Latch 92 (which may be implemented as aset-reset latch or other suitable circuit or logic device) may generatecontrol signals P_(x) (e.g., control signals P₁, P₂, P₃, etc.) and

(e.g., control signals

,

,

, etc.) for controlling switches of boost converter 20 as shown in FIG.5 . For example, when inductor current I_(L) falls below valley currentthreshold I_(val), latch 92 may assert control signal P_(x) and deassertcontrol signal

, and when inductor current I_(L) falls below valley current thresholdL_(val), latch 92 may deassert control signal P_(x) and assert controlsignal

.

While the foregoing hysteretic boost converter 20 described andillustrated above may be effective in overcoming the disadvantages ofmany existing approaches to power converters, the systems and methodsdescribed above may have shortcomings for very low duty cycles of boostconverter 20. To demonstrate these potential shortcomings, FIG. 17Aillustrates a graph of an example waveform for boost converter inductorcurrent I_(L) for typical duty cycles of boost converter 20 (e.g., whenthe ratio of supply voltage V_(SUPPLY) to voltage VDD_SENSE issignificantly greater than 1), in accordance with embodiments of thepresent disclosure, while FIG. 17B illustrates graphs of examplewaveforms for boost converter inductor current I_(L) for very low dutycycles of boost converter 20 (e.g., when the ratio of supply voltageV_(SUPPLY) to voltage VDD_SENSE approaches 1), in accordance withembodiments of the present disclosure. As is shown in FIGS. 17A and 17B,during a transfer state of boost converter 20, a negative slope (withrespect to time) of inductor current I_(L) may be determined by thedifference between supply voltage V_(SUPPLY) and voltage VDD_SENSE, andas the ratio of supply voltage V_(SUPPLY) to voltage VDD_SENSEapproaches 1, the negative slope becomes increasingly shallow (e.g.,smaller in magnitude). This decreasing-magnitude slope occurs as aresult of a duty cycle of boost converter 20 becoming smaller (e.g.,duty cycles of control signals P_(x) becoming smaller), as boostconverter 20 spends decreasing amounts of time in the charging state andincreasing amounts of time in the transfer state as the ratio of supplyvoltage V_(SUPPLY) to voltage VDD_SENSE approaches 1. As a result, it ispossible that for some values of voltage VDD_SENSE, inductor currentI_(L) may never decrease to the valley current threshold I_(val),resulting in a potentially infinite transfer state, which may furtherlead to inductor current I_(L) reaching a steady-state value betweenpeak current threshold I_(pk) and valley current threshold I_(val).

Such increased transfer states in response to decreased duty cycles maycause undesirable sag in supply voltage V_(SUPPLY), particularly duringhigh-loading scenarios at the output of boost converter 20. Todemonstrate, FIG. 18A illustrates graphs of example waveforms for anoutput current load current I_(LOAD) of boost converter 20, boostconverter inductor current I_(L), and supply voltage V_(SUPPLY)generated by boost converter 20 for typical duty cycles of boostconverter 20 in response to a step in load current I_(LOAD), inaccordance with embodiments of the present disclosure. FIG. 18Billustrates graphs of example waveforms for output current load currentI_(LOAD) of boost converter 20, boost converter inductor current I_(L),and supply voltage V_(SUPPLY) generated by boost converter 20 for verylow duty cycles of boost converter 20 in response to a step in loadcurrent I_(LOAD), in accordance with embodiments of the presentdisclosure.

As described above, an increase in load current I_(LOAD) may cause loadestimator 44 in concert with current controller 46 to increase load toincrease peak current threshold I_(pk) and valley current thresholdI_(val), as shown in each of FIGS. 18A and 18B. Such increase typicallyincreases an average current delivered to the electrical node of supplyvoltage V_(SUPPLY), thus maintaining regulation of supply voltageV_(SUPPLY), as shown in FIG. 18A. However, as the ratio of supplyvoltage V_(SUPPLY) to voltage VDD_SENSE approaches 1 (or stated anotherway, as voltage VDD_SENSE approaches supply voltage V_(SUPPLY)),decrease in duty cycle of boost converter 20 may lead to a scenarioshown in FIG. 18B in which inductor current I_(L) never decreases tovalley current threshold I_(val), meaning inductor current I_(L) maycease to be regulated by peak current threshold I_(pk) and valleycurrent threshold I_(val). As a result, the average current delivered tothe electrical node of supply voltage V_(SUPPLY) may not increase duringthe step increase of load current I_(LOAD), which means boost converter20 may cease to regulate supply voltage V_(SUPPLY), leading to anundesirable sag in supply voltage V_(SUPPLY).

FIG. 19 illustrates a block diagram of selected components of an examplepeak/valley controller 48B with further improvements over peak/valleycontroller 48A of FIG. 16 , in accordance with embodiments of thepresent disclosure. In some embodiments, peak/valley controller 48B maybe used to implement peak/valley controller 48 shown in FIG. 5 .Further, peak/valley controller 48B shown in FIG. 19 may be similar inmany respects to peak/valley controller 48A shown in FIG. 16 , and thusonly certain differences between peak/valley controller 48B andpeak/valley controller 48A are described below. Peak-valley controller48B may be implemented in analog circuitry, digital circuitry, or acombination thereof.

FIG. 20 illustrates graphs of example waveforms for load currentI_(LOAD) of boost converter 20, boost converter inductor current I_(L),a counter internally maintained by timer 94, force signal FORCEgenerated by timer 94, and control signal P_(x) for very low duty cyclesof boost converter 20 using the example peak/valley controller 48B inresponse to a step in load current I_(LOAD), in accordance withembodiments of the present disclosure.

One difference between peak/valley controller 48B and peak/valleycontroller 48A is that peak/valley controller 48B may include a timer 94configured to hold in reset when control signal P_(x) is asserted (e.g.,when control signal P_(x) is high). When control signal P_(x) isdeasserted (i.e., when boost converter 20 enters its transfer state),timer 94 may begin timing a duration of the transfer state. If thetransfer state exceeds a predetermined maximum duration, timer 94 mayassert a force signal FORCE.

As also shown in FIG. 19 , peak/valley controller 48B may include alogical OR gate 96 that performs a logical OR operation of the output ofcomparator 90A with force signal FORCE. As a result, if, after the startof a transfer state of boost converter 20, inductor current I_(L) failsto decrease to valley current threshold I_(val) within the predeterminedmaximum duration of timer 94, timer 94 may assert force signal FORCE toforce an end to the transfer state and begin a new charging state.Accordingly, even if inductor current I_(L) fails to decrease to valleycurrent threshold I_(val), boost converter 20 is still able toperiodically increase inductor current I_(L), and thus, cause inductorcurrent I_(L) to periodically reach peak current threshold I_(pk) suchthat inductor current I_(L) may be regulated by peak current thresholdI_(pk), in turn allowing boost converter 20 to maintain current controland regulation of supply voltage V_(SUPPLY),

One potential disadvantage of peak/valley controller 48B may occur indigital implementations of some or all of the components of peak/valleycontroller 48B. To illustrate, in peak/valley controller 48B, controlsignal P_(x) may be converted to a discrete time signal using azero-order-hold circuit (e.g., a synchronizer, series of latches, etc.).In such a digital implementation, if a pulse width of control signalP_(x) is less than one digital sampling period, the digital circuitryimplementing peak/valley controller 48B may fail to detect such pulse.

FIG. 21 illustrates a block diagram of selected components of an examplepeak/valley controller 48C with further improvements over peak/valleycontroller 48B of FIG. 19 , in accordance with embodiments of thepresent disclosure. In some embodiments, peak/valley controller 48C maybe used to implement peak/valley controller 48 shown in FIG. 5 .Further, peak/valley controller 48C shown in FIG. 21 may be similar inmany respects to peak/valley controller 48B shown in FIG. 19 , and thusonly certain differences between peak/valley controller 48C andpeak/valley controller 48B are described below.

As shown in FIG. 21 , in addition to those components of peak/valleycontroller 48B, peak/valley controller 48C may include a secondset-reset latch 98 and a zero-order hold circuit 99. In operation, theset input of set-reset latch 98 may receive control signal P_(x). Evenif control signal P_(x) is of short duration, set-reset latch 98 mayassert its output Q until set-reset latch 98 is reset. Once the output Qof set-reset latch 98 is asserted, a digital subsystem comprising timer94 and zero-order hold circuit 99 may measure output Q of set-resetlatch 98 during its next clock cycle using zero-order hold circuit 99.The sampled output of zero-order hold circuit 99 may be received bytimer 94 in order to reset timer 94, and such sampled output may also bereceived by the reset input of set-reset latch 98 in order to serve asan acknowledge signal ACK to reset set-reset latch 98. Accordingly, theinclusion of second set-reset latch 98 and zero-order hold circuit 99may ensure that timer 94 does not miss any pulses of control signalP_(x). As a possible variation to the embodiments represented by FIG. 21, in some embodiments, set-reset latch 98 may be configured as aset-dominant latch to prevent unnecessary toggling of its output shouldcontrol signal P_(x) remain asserted for more than one digital clockcycle.

One potential disadvantage of peak/valley controller 48C may result fromprocessing delays which may delay force signal FORCE and acknowledgesignal ACK by one or more digital clock signals. Due to such delay,control signal P_(x) may be asserted for too long, potentially causingovershoot of inductor current I_(L) well above peak current thresholdI_(pk). Such overshoot may result in inductor saturation and damage tocircuitry of boost converter 20.

FIG. 22 illustrates a block diagram of selected components of an examplepeak/valley controller 48D with further improvements over peak/valleycontroller 48C of FIG. 21 , in accordance with embodiments of thepresent disclosure. In some embodiments, peak/valley controller 48D maybe used to implement peak/valley controller 48 shown in FIG. 5 .Further, peak/valley controller 48D shown in FIG. 22 may be similar inmany respects to peak/valley controller 48C shown in FIG. 21 , and thusonly certain differences between peak/valley controller 48D andpeak/valley controller 48C are described below.

As shown in FIG. 22 , in addition to those components of peak/valleycontroller 48C, peak/valley controller 48D may include a logical ANDgate 97. Logical AND gate 97 may perform a logical AND operation offorce signal FORCE and the complementary output Q of set-reset latch 98logically inverted by inverter 95. As a result, logical AND gate 97 maymask out any erroneous assertions of force signal FORCE that may resultfrom digital processing delays of any digital circuitry used toimplement peak/valley controller 48D.

As used herein, when two or more elements are referred to as “coupled”to one another, such term indicates that such two or more elements arein electronic communication or mechanical communication, as applicable,whether connected indirectly or directly, with or without interveningelements.

This disclosure encompasses all changes, substitutions, variations,alterations, and modifications to the example embodiments herein that aperson having ordinary skill in the art would comprehend. Similarly,where appropriate, the appended claims encompass all changes,substitutions, variations, alterations, and modifications to the exampleembodiments herein that a person having ordinary skill in the art wouldcomprehend.

Moreover, reference in the appended claims to an apparatus or system ora component of an apparatus or system being adapted to, arranged to,capable of, configured to, enabled to, operable to, or operative toperform a particular function encompasses that apparatus, system, orcomponent, whether or not it or that particular function is activated,turned on, or unlocked, as long as that apparatus, system, or componentis so adapted, arranged, capable, configured, enabled, operable, oroperative. Accordingly, modifications, additions, or omissions may bemade to the systems, apparatuses, and methods described herein withoutdeparting from the scope of the disclosure. For example, the componentsof the systems and apparatuses may be integrated or separated. Moreover,the operations of the systems and apparatuses disclosed herein may beperformed by more, fewer, or other components and the methods describedmay include more, fewer, or other steps. Additionally, steps may beperformed in any suitable order. As used in this document, “each” refersto each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in the figures anddescribed below, the principles of the present disclosure may beimplemented using any number of techniques, whether currently known ornot. The present disclosure should in no way be limited to the exemplaryimplementations and techniques illustrated in the drawings and describedabove.

Unless otherwise specifically noted, articles depicted in the drawingsare not necessarily drawn to scale.

All examples and conditional language recited herein are intended forpedagogical objects to aid the reader in understanding the disclosureand the concepts contributed by the inventor to furthering the art, andare construed as being without limitation to such specifically recitedexamples and conditions. Although embodiments of the present disclosurehave been described in detail, it should be understood that variouschanges, substitutions, and alterations could be made hereto withoutdeparting from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, variousembodiments may include some, none, or all of the enumerated advantages.Additionally, other technical advantages may become readily apparent toone of ordinary skill in the art after review of the foregoing figuresand description.

To aid the Patent Office and any readers of any patent issued on thisapplication in interpreting the claims appended hereto, applicants wishto note that they do not intend any of the appended claims or claimelements to invoke 35 U.S.C. § 112(f) unless the words “means for” or“step for” are explicitly used in the particular claim.

1. A method for controlling a current associated with a power converter,comprising: controlling the current based on at least a peak currentthreshold level for the current and a valley current threshold level forthe current; and further controlling the current based on a duration oftime that the power converter spends in a switching state of the powerconverter.
 2. The method of claim 1, further comprising switching thepower converter between a charging state in which the current increasesand a transfer state in which the current decreases.
 3. The method ofclaim 2, further comprising switching the power converter between thetransfer state and the charging state based on the duration of time. 4.The method of claim 3, wherein the duration of time comprises a durationof time of the transfer state, and the method further comprisesswitching the power converter from the transfer state to the chargingstate if the duration of time exceeds a threshold duration.
 5. Themethod of claim 1, further comprising measuring the duration of timewith a timer.
 6. The method of claim 5, further comprising resetting thetimer at the start of the switching state.
 7. The method of claim 6,wherein the switching state is a transfer state of the power converterin which the current decreases. 8.-11. (canceled)
 12. A control circuitfor controlling a current associated with a power converter, the controlcircuit comprising: threshold-based control circuitry configured tocontrol the current based on at least a peak current threshold level forthe current and a valley current threshold level for the current; andtimer-based control circuitry configured to control the current based ona duration of time that the power converter spends in a switching stateof the power converter.
 13. The control circuit of claim 12, wherein thecontrol circuit is configured to switch the power converter between acharging state in which the current increases and a transfer state inwhich the current decreases.
 14. The control circuit of claim 13,wherein the timer-based control circuitry is configured to switch thepower converter between the transfer state and the charging state basedon the duration of time.
 15. The control circuit of claim 14, whereinthe duration of time comprises a duration of time of the transfer state,and the timer-based control circuitry is configured to switch the powerconverter from the transfer state to the charging state if the durationof time exceeds a threshold duration.
 16. The control circuit of claim12, wherein the timer-based control circuitry is further configured tomeasure the duration of time with a timer.
 17. The control circuit ofclaim 16, wherein the timer-based control circuitry is furtherconfigured to reset the timer at the start of the switching state. 18.The control circuit of claim 17, wherein the switching state is atransfer state of the power converter in which the current decreases.19.-22. (canceled)
 23. A device comprising: a power converter; and acontrol circuit for controlling a current associated with the powerconverter, the control circuit comprising: threshold-based controlcircuitry configured to control the current based on at least a peakcurrent threshold level for the current and a valley current thresholdlevel for the current; and timer-based control circuitry configured tocontrol the current based on a duration of time that the power converterspends in a switching state of the power converter.